Gain-Cell Embedded Drams for Low-Power VLSI Systems-On-Chip Softcover Repri Edition Contributor(s): Meinerzhagen, Pascal (Author), Teman, Adam (Author), Giterman, Robert (Author) |
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ISBN: 3319868551 ISBN-13: 9783319868554 Publisher: Springer OUR PRICE: $113.99 Product Type: Paperback - Other Formats Published: May 2018 |
Additional Information |
BISAC Categories: - Technology & Engineering | Electronics - Circuits - General - Computers | Hardware - General |
Dewey: 004.53 |
Physical Information: 0.34" H x 6.14" W x 9.21" (0.51 lbs) 146 pages |
Descriptions, Reviews, Etc. |
Publisher Description: This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. |