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Assertion-Based Design 2004 Edition
Contributor(s): Foster, Harry D. (Author), Krolnik, Adam C. (Author), Lacey, David J. (Author)
ISBN: 1402080271     ISBN-13: 9781402080272
Publisher: Springer
OUR PRICE:   $161.49  
Product Type: Hardcover - Other Formats
Published: May 2004
Qty:
Annotation: The focus of Assertion-Based Design, Second Edition is three-fold:

-How to specify assertions,
-How to create and adopt a methodology that supports assertion-based design (predominately for RTL design),
-What to do with the assertions and methodology once you have them. To support these three over-arching goals, we showcase multiple forms of assertion specifications: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera System Verilog.
The recommendations and claims we make in this book are based on our combined actual experiences in applying an assertion-based methodology to real design and verification as well as our work in developing industry assertion standards.
Differences between the first edition and the second edition include:

-Updates to the manuscript based on newer versions of standards,
-Corrections to errata identified during reviewer feedback,
-New material that presents techniques on how to avoid common ambiguity errors,
-New material that discusses high-level requirements modeling for specification.
Additional Information
BISAC Categories:
- Computers | Logic Design
- Computers | Cad-cam
Dewey: 621.395
LCCN: 2004042136
Series: Information Technology: Transmission, Processing & Storage
Physical Information: 1.08" H x 6.22" W x 9.6" (1.81 lbs) 390 pages
 
Descriptions, Reviews, Etc.
Publisher Description:
Chapter 3 Specifying RTL Properties 61 3. 1 Definitions and concepts 62 62 3. 1. 1 Property 3. 1. 2 Events 65 3. 2 Property classification 65 Safety versus liveness 66 3. 2. 1 3. 2. 2 Constraint versus assertion 67 3. 2. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 3. 1 3. 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3. 3 3. 3. 4 PSL and default clock declaration 74 3. 3. 5 Specifying sequences 75 3. 3. 6 Specifying eventualities 80 3. 3. 7 PSL built-in functions 82 3. 4Pragma-based assertions 82 3. 5 SystemVerilog assertions 84 3. 5. 1 Immediate assertions 84 3. 5. 2Concurrent assertions 86 3. 5. 3 System functions 95 3. 6 PCI property specification example 96 3. 6. 1 PCI overview 96 3. 7 Summary 102 Chapter 4 PLI-Based Assertions 103 4. 1 Procedural assertions 104 4. 1. 1 A simple PLI assertion 105 4. 1. 2 Assertions within a simulation time slot 108 4. 1. 3 Assertions across simulation time slots 111 4. 1. 4 False firing across multiple time slots 116 4. 2 PLI-based assertion library 118 4. 2. 1 Assert quiescent state 119 4. 3 Summary 123 Chapter 5 Functional Coverage 125 5. 1 Verification approaches 126 5. 2 Understanding coverage 127 5. 2. 1 Controllability versus observability 128 5. 2.