| Hardware/Software Co-Design for Data Flow Dominated Embedded Systems Contributor(s): Niemann, Ralf (Author), Marwedel, Peter (Foreword by) |
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ISBN: 1441950648 ISBN-13: 9781441950642 Publisher: Springer OUR PRICE: $161.49 Product Type: Paperback - Other Formats Published: December 2010 |
| Additional Information |
| BISAC Categories: - Technology & Engineering | Electronics - Circuits - General - Computers | Software Development & Engineering - Systems Analysis & Design - Computers | Cad-cam |
| Dewey: 004.21 |
| Physical Information: 0.51" H x 6.14" W x 9.21" (0.76 lbs) 224 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: Many of the modern applications of microelectronics require hugeamounts of computations. Despite all recent improvements in fabrication technologies, some of these computations have to be performed in hardware in order to meet deadlines. However, controlling computations by software is frequently pre- ferred due to the larger flexibility. Hence, in general, modern applications re- quire a mix of software-based and hardware-based computations. Applications using this mix can be designed with the help of hardware/software co-design systems. Many such co-design systems have been described so far (references can be found in this book), but many of these are based on heuristics. In this book, Niemann describes a co-design system which is based on sound modeling techniques. This system has the following salient features: - Precise cost and performance figures Design decisions for implementing a certain function in hardware or software are based on 'cost and performance figures for the different design alterna- tives. Hence, good designs can only be expected if these figures are accurate. In order to achieve excellent accuracy, Niemann takes a new approach: the cost of software implementations is derived from the data available about the target processors and from knowledge about the code size. the performance of software implement at ions is computed by compiling the given function and then using static analysis for computing worst case execution times. the cost of hardware implementation is estimated by running higher-Ievel synthesis tools. the performance of hardware implementations is again computed by us- ing static analysis. |