| Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS 2014 Edition Contributor(s): Noia, Brandon (Author), Chakrabarty, Krishnendu (Author) |
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ISBN: 3319023772 ISBN-13: 9783319023779 Publisher: Springer OUR PRICE: $104.49 Product Type: Hardcover - Other Formats Published: December 2013 |
| Additional Information |
| BISAC Categories: - Computers | Systems Architecture - General - Technology & Engineering | Electronics - Semiconductors - Computers | Hardware - Mainframes & Minicomputers |
| Dewey: 004.1 |
| Physical Information: 0.8" H x 6" W x 9.2" (1.45 lbs) 245 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. |