Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc Contributor(s): Coppola, Marcello (Author), Grammatikakis, Miltos D. (Author), Locatelli, Riccardo (Author) |
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ISBN: 1420044710 ISBN-13: 9781420044713 Publisher: CRC Press OUR PRICE: $133.00 Product Type: Hardcover - Other Formats Published: October 2008 Annotation: Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: "Spidergon STNoC" comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment. |
Additional Information |
BISAC Categories: - Computers | Microprocessors - Computers | Hardware - Mainframes & Minicomputers - Technology & Engineering | Electronics - Microelectronics |
Dewey: 004.12 |
LCCN: 2008026558 |
Series: System-On-Chip Design and Technologies |
Physical Information: 1" H x 6.4" W x 9.3" (1.45 lbs) 288 pages |
Descriptions, Reviews, Etc. |
Publisher Description: Streamlined Design Solutions Specifically for NoC A Balanced Analysis of NoC Architecture
From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns. |